The present invention relates to a hetero junction type bipolar transistor and a fabrication method thereof, and more particularly to a measure to improve a linearity of current characteristics.
Recently, the development has been advancing at a high pitch for a hetero bipolar transistor (HBT) that realizes an operation at a high frequency region with better conduction characteristics conferred by incorporating a hetero junction structure, such as Si/SiGe and Si/SiC, into a bipolar transistor fabricated on a silicon substrate. The HBT uses a Si/SiGe hetero junction structure obtained by allowing epitaxial growth of a SiGe layer on a Si substrate, so that it realizes a transistor operating at a high frequency region at which a conventional transistor cannot operate unless it uses a compound semiconductor substrate, such as GaAs. The HBT is made of materials having a good affinity for a general silicon process, such as a Si substrate and a SiGe layer, which provides remarkable advantages in achieving high integration and a low cost. In particular, integrating a HBT and a MOS transistor (MOSFET) by forming the both on a common Si substrate makes it possible to fabricate a high-performance BiCMOS device. Moreover, the BiCMOS device is expected to serve as a system LSI applicable to communication systems.
FIG. 10 is a cross section showing a structure of a conventional HBT. As is shown in the drawing, a top portion of a Si substrate 500 having a (001) plane forms a retrograde well 501 with a depth of 1 xcexcm including a N-type impurity, such as phosphorous, introduced by the epitaxial growth method, ion implantation method, etc. Also, for the isolation, provided are a shallow trench 503 filled with silicon oxide and a deep trench 504 formed from an undoped polysilicon film 505 and a silicon dioxide film 506 surrounding the same. The trenches 503 and 504 have depths of approximately 0.35 xcexcm and 2 xcexcm, respectively.
Also, a collector layer 502 is provided in the Si substrate 500 at a region sandwiched by the trenches 503, and a N+ collector connecting layer 507 is provided in the Si substrate 500 at a region separated from the collector layer 502 by the shallow trench 503 for establishing a contact with an electrode of the collector layer 502 through the retrograde well 501.
Also, a first deposited oxide film 508 with a thickness of approximately 30 nm having a collector opening portion 510 is formed on the Si substrate 500, and a Si/Si1-xGex layer 511 is formed by depositing a Si1-xGex layer doped with a P-type impurity with a thickness of approximately 60 nm and a Si film with a thickness of approximately 10 nm on the top surface of the Si substrate 500 at a portion exposed to the collector opening portion 510. The bottom portion of the Si/Si1-xGex layer 511 at the center thereof (a region below a base opening portion 518, which will be described bellow) functions as an intrinsic base 519. On the other hand, the top portion of the Si/Si1-xGex layer 511 at the center thereof functions as an emitter layer.
A second deposited oxide film 512 with a thickness of approximately 30 nm to serve as an etch stopper is provided on the Si/Si1-xGex layer 511 and the first deposited oxide film 508, and the second deposited oxide film 512 is provided with a base junction opening portion 514 and a base opening portion 518. Provided next are a P+ polysilicon layer 515 with a thickness of approximately 150 nm that fills in the base junction opening portion 514 and extends over the second deposited oxide film 512, and a third deposited oxide film 517. An extrinsic base 516 is constructed by the Si/Si1-xGex layer 511 except for the region below the base opening portion 518 and the P+ polysilicon layer 515.
Also, the P+ polysilicon layer 515 and the third deposited oxide film 517 are opened at portions positioned above the base opening portion 518 in the second deposited oxide film 512, and a fourth deposited oxide film 520 with a thickness of approximately 30 nm is formed on the side surface of the P+ polysilicon layer 515. Further, a sidewall 521 made of polysilicon with a thickness of approximately 100 nm is provided on the fourth deposited oxide film 520. Then, an N+ polysilicon layer 529 is provided to fill the base opening portion 518 and to extend over the third deposited oxide film 517, and the N+ polysilicon layer 529 thus functions as an emitter connecting electrode. The fourth deposited oxide film 520 not only electrically isolates the P+ polysilicon layer 515 from the N+ polysilicon layer 529, but also prevents out-diffusion of the impurity from the P+ polysilicon layer 515 into the N+ polysilicon layer 529. Also, the third deposited oxide film 517 electrically isolates the top surface of the P+ polysilicon layer 515 from the N+ polysilicon layer 529.
Further, a Ti silicide layer 524 is formed on the surfaces of the collector connecting layer 507, P+ polysilicon layer 515, and N+ polysilicon layer 529, and the outside sidewalls of the N+ polysilicon layer 529 and the P+ polysilicon layer 515 are covered with a sidewall 523. The entire substrate is covered with an inter-layer insulator film 525, through which contact holes that respectively reach the Ti silicide layer 524 formed on the N+ collector connecting layer 507, P+ polysilicon layer 515 as a part of the extrinsic base, and N+ polysilicon layer 529 functioning as the emitter connecting electrode are provided. Then, each contact hole is filled with a W plug 526 and is provided with a metal wiring 527 connected to the W plug 526 and extending over the inter-layer insulator film 525.
However, the above-discussed conventional HBT or SiGe-BiCMOS has problems as follows.
FIG. 11(a) is a view showing dependencies of a base current and a collector current on a base-emitter voltage, that is, so-called Gummel characteristics of the conventional HBT. In the drawing, the horizontal axis represents the base-emitter voltage (V), and the vertical axis represents the base current or collector current (A) (logarithmic scales). As is shown in the drawing, the parallel relation between the collector current characteristics curve and the base current characteristics curve is lost at a low base-emitter voltage region, and there is an excessive base current. In short, there is an inconvenience that the linearity of the current characteristics is deteriorated in the low bias region of the HBT.
Causes of such an inconvenience are checked, and one of the causes is found to be a recombination current generated excessively at a region underneath the second deposited oxide film 112 in the Si layer. It is assumed that such an excessive recombination current is generated because a depletion layer at the pn junction region in the Si layer is not formed in a satisfactory shape.
FIGS. 12(a) and 12(b) are an enlarged partial cross section showing an emitter-base junction region in the conventional HBT, and a doping profile of boron along a cross section in the vicinity of the emitter-base junction region, respectively. As shown in FIG. 12(a), the Si/Si1-xGex layer 511 is formed by sequentially depositing an undoped SiGe spacer layer 551 with a Ge content of 15%, a P-type graded SiGe base layer 552 including boron at a high concentration with a Ge content continuously changing from 15% at the lower end to 0% at the upper end, and an undoped Si-cap layer 553. The Si-cap layer 553 is provided with an N-type emitter diffusion layer 553a formed by introducing phosphorous out-diffused from the N+ polysilicon layer 529 (emitter connecting electrode) at a high concentration at a region directly below the base opening portion 518 and in contact with the N+ polysilicon layer 529. Then, a peripheral layer 553b (especially, the bottom portion) of the Si-cap layer 511 surrounding the emitter diffusion layer 553a includes boron out-diffused from the graded SiGe layer 552, which makes the peripheral layer 553b into the P-type. Hence, there is a pn junction region between the emitter diffusion layer 553a and the peripheral layer 553b in the Si-cap layer 551, and a depletion layer 554 expands along the both sides of the metallurgical pn junction interface in the pn junction region. At this point, the depletion layer 554 has a broader width in the upper part of the Si-cap layer 551. Hence, a recombination current generated from carriers recombined within the depletion layer 554 increases, which is assumed to cause deterioration in the linearity of the current characteristics as shown in FIG. 11(a).
According to Physics of Semiconductor Devices, S. M. Sze, John Wiley and Sons, Inc., 1981, pp. 89-94, the recombination current Irec is expressed as:
Irec=S∫qxc2x7Uxc2x7dx (x=0 to W),
where S is the area of the pn junction, W is the depletion layer width, U is a recombination rate, and q is the elemental charge.
Here, the recombination rate U is determined by parameters of deep level traps in the depletion layer, such as densities at deep level traps, depths of the levels of the traps, the capture cross sections of the traps, and so on. The above expression indicates that a recombination current increases as the width of the depletion layer (a distance from the first depletion layer end to the second depletion layer end) broadens, because deep level traps in the depletion region between a first depletion layer edge and a second depletion layer edge in FIG. 12(a) work as recombination centers.
In other words, as shown in FIG. 12(a), according to the conventional bipolar transistor discussed above, it is assumed that the recombination current Irec increases because the depletion region 554 becomes wider particularly in the upper part of the Si-cap layer 551.
In view of the foregoing, the present invention has an object to provide a bipolar transistor having a satisfactory linearity of the current characteristics and a fabrication method thereof by taking a means to improve a doping profile of an impurity in the Si-cap layer in the HBT.
In order to reduce the recombination current Irec by reducing the width of the depletion layer, the present invention takes means as follows.
A bipolar transistor of the present invention includes: a first semiconductor layer to be a collector layer formed on a substrate and including an impurity of a first conductive type; a second semiconductor layer to be a base layer formed on the first semiconductor layer and including an impurity of a second conductive type; a third semiconductor layer formed on the second semiconductor layer from a material having a bandgap different from a bandgap of the second semiconductor layer; an insulator film provided on the third semiconductor layer; an opening portion formed through the insulator film to reach the third semiconductor layer; and an emitter connecting electrode made of a conductor material and brought into contact with the third semiconductor layer by filling the opening portion in the insulator film, wherein the third semiconductor layer includes an emitter diffusion layer of the first conductive type positioned below the opening portion, and a peripheral layer including the impurity of the second conductive type at least in an upper part thereof at a region located at a side of the emitter diffusion layer.
Accordingly, the pn junction portion is formed between the emitter diffusion layer including the impurity of the first conductive type at a high concentration and the third semiconductor layer including the impurity of the second conductive type at a high concentration in the upper part of the third semiconductor layer. Hence, the width of the depletion layer formed at the pn junction is narrowed, and a quantity of carriers recombined within the depletion layer is reduced. Consequently, because the recombination current is reduced, the linearity of the current characteristics in a hetero junction type bipolar transistor is improved.
It may be arranged in such a manner that the insulator film is formed from a silicon dioxide film doped with the impurity of the second conductive type, and the impurity of the second conductive type included in at least a part of the upper part of the third semiconductor layer is the impurity of the second conductive type out-diffused from the insulator film.
It may be arranged in such a manner so as to further include a polysilicon film, doped with the impurity of the second conductive type and provided so as to contact the third semiconductor layer at a portion outside of the underlying insulator film and to extend over the insulator film, for functioning as a base connecting electrode, so that the impurity of the second conductive type included in at least a part of the upper part of the third semiconductor layer is the impurity of the second conductive type out-diffused from the polysilicon film by passing through the insulator film.
By arranging in such a manner that the impurity of the first conductive type in the emitter diffusion layer of the third semiconductor layer is the impurity of the first conductive type out-diffused from the emitter connecting electrode, it is possible to obtain an emitter diffusion layer using inversion of the conductive types in the third semiconductor layer.
By arranging in such a manner that: the substrate is a silicon substrate; the first semiconductor layer is a Si layer; the second semiconductor layer is a SiGe layer or a SiGeC layer; and the third semiconductor layer is a Si layer, it is possible to obtain a SiGe-HBT that can be readily fabricated by using the Si process.
A first bipolar transistor of the present invention includes: a step (a) of forming a second semiconductor layer to be a base layer including a second conductive type impurity on a first semiconductor layer that is formed on a substrate to be a collector layer including a first conductive type impurity; a step (b) of forming, on the second semiconductor layer, a third semiconductor layer, including the second conductive type impurity at least at an upper part thereof, through epitaxial growth from a material having a bandgap different from a bandgap of the second semiconductor layer; a step (c) of depositing an insulator film on the substrate after the step (b); a step (d) of forming an opening portion through the insulator film, to reach the third semiconductor layer; and a step (e) of forming an emitter diffusion layer in the third semiconductor layer at a region below the opening portion by introducing the first conductive type impurity.
According to this method, it is possible to control a concentration of the second conductive type impurity doped into the upper part of the third semiconductor layer at a relatively high accuracy by conducting in-situ doping in the third semiconductor layer.
A second fabrication method of a bipolar transistor of the present invention includes: a step (a) of forming a second semiconductor layer to be a base layer including a second conductive type impurity on a first semiconductor layer that is formed on a substrate to be a collector layer including a first conductive type impurity; a step (b) of forming, on the second semiconductor layer, a third semiconductor layer through epitaxial growth from a material having a bandgap different from a bandgap of the second semiconductor layer; a step (c) of depositing an insulator film including the second conductive type impurity on the substrate after the step (b); a step (d) of forming an opening portion through the insulator film to reach the third semiconductor layer; and a step (e) of forming an emitter diffusion layer in the third semiconductor layer at a region below the opening portion by introducing the first conductive type impurity, so that the second conductive type impurity is doped into an upper part of the third semiconductor layer from the insulator film by treatments after the step (c).
According to this method, it is possible to dope the second conductive type impurity into the upper part of the third semiconductor layer by relatively simple steps.
A third fabrication method of a bipolar transistor of the present invention includes: a step (a) of forming a second semiconductor layer to be a base layer including a second conductive type impurity on a first semiconductor layer that is formed on a substrate to be a collector layer including a first conductive type impurity; a step (b) of forming, on the second semiconductor layer, a third semiconductor layer through epitaxial growth from a material having a bandgap different from a bandgap of the second semiconductor layer; a step (c) of depositing an insulator film on the substrate after the step (b); a step (d) of depositing a conductor film including the second conductive type impurity on the substrate and forming an opening portion through the conductor film to reach the insulator film; a step (e) of forming a sidewall made of an insulating material for covering a side surface of the opening portion in the first conductor film; a step (f) of forming an opening portion through the insulator film to reach the third semiconductor layer after the step (e); and a step (g) of forming an emitter diffusion layer in the third semiconductor layer at a region located below the opening portion by introducing the first conductive type impurity, so that the second conductive type impurity is doped into an upper part of the third semiconductor layer from the conductor film by passing through the insulator film by treatments after the step (d).
According to this method, it is possible to dope the second conductive type impurity into the upper part of the third semiconductor layer only at a region excluding a region that will be made into an emitter diffusion layer. Hence, a concentration of the second conductive type impurity can be set as desired regardless of a concentration of the first conductive type impurity in the emitter diffusion layer.
By further including, after the step (f) and before the step (g), a step of depositing, on the substrate, another conductor film different from the above conductor film, and then patterning this another conductor film to form an emitter connecting electrode including the first conductive type impurity in such a manner so as to fill in the opening portion in the insulator film and to extend over the insulator film, it is possible to fabricate a HBT by using the double-polysilicon sequence.